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publication# 17469 rev. e amendment /0 issue date: may 1995 mach435-12/15/20, q-20/25 high-density ee cmos programmable logic final com'l: -12/15/20, q-20/25 distinctive characteristics n 84 pins in plcc n 128 macrocells n 12 ns t pd n 83.3 mhz f cnt n 70 inputs with pull-up resistors n 64 outputs n 192 flip-flops 128 macrocell flip-flops 64 input flip-flops n up to 20 product terms per function, with xor n flexible clocking four global clock pins with selectable edges asynchronous mode available for each macrocell n 8 pal33v16 blocks n input and output switch matrices for high routability n fixed, predictable, deterministic delays n pin compatible with mach130, mach131, mach230, and mach231 general description t h e m a c h 4 3 5 i s a m e m b e r o f o u r h i g h - p e r f o r m a n c e ee cmos mach 4 family. this device has approxi- mately twelve times the macrocell capability of the popular pal22v10, with significant density and func- tional features that the pal22v10 does not provide. the mach435 consists of eight pal blocks intercon- nected by a programmable central switch matrix. the central switch matrix connects the pal blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected pal blocks. this allows designs to be placed and routed efficiently. routability is further enhanced by an input switch matrix and an output switch matrix. the input switch matrix provides input signals with alternative paths into the central switch matrix; the output switch matrix provides flexibility in assigning macrocells to i/o pins. the mach435 has macrocells that can be configured as synchronous or asynchronous. this allows designers to implement both synchronous and asynchronous logic together on the same device. the two types of design can be mixed in any proportion, since the selection on each macrocell affects only that macrocell. up to 20 product terms per function can be assigned. it is possible to allocate some product terms away from a macrocell without losing the use of that macrocell for logic generation. the mach435 macrocell provides either registered or combinatorial outputs with programmable polarity. if a registered configuration is chosen, the register can be configured as d-type, t-type, j-k, or s-r to help reduce the number of product terms used. the flip-flop can also be configured as a latch. the register type decision can be made by the designer or by the software. all macrocells can be connected to an i/o cell through the output switch matrix. the output switch matrix makes it possible to make significant design changes while minimizing the risk of pinout changes. lattice semiconductor
2 mach435-12/15/20, q-20/25 block diagram 17469e-1 central switch matrix 4 4 2 clk0/i0, clk1/i1, clk2/i3, clk3/i4 i2, i5 i/o0?/o7 i/o8?/o15 i/o16?/o23 i/o24?/031 i/o32?/o39i/o40?/o47i/o48?/o55i/o56?/o63 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator input switch matrix 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator input switch matrix 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator input switch matrix 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator oe 16 16 24 16 16 8 33 4 4 4 8 8 input switch matrix input switch matrix input switch matrix clock generator clock generator clock generator input switch matrix input switch matrix clock generator oe oe oe oe oe oe oe
3 mach435-12/15/20, q-20/25 connection diagram top view 17469e-2 plcc 1 2 3 81 82 83 84 6 7 8 9 4 5 80 76 77 78 79 75 12 13 14 15 16 17 18 19 20 21 23 24 25 26 27 28 29 30 31 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 43 42 41 40 47 46 45 44 37 36 35 34 39 38 33 48 52 51 50 49 10 22 11 32 53 74 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 clk 0 /i 0 v cc gnd clk 1 /i 1 i/o16 i/o17 i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 gnd i/o8 gnd i/o55 i/o54 i/o53 i/o52 i/o51 i/o50 i/o49 i/o48 clk 3 /i 4 v cc clk 2 /i 3 i/o47 i/o46 i/o45 i/o44 i/o43 i/o42 i/o41 gnd i/o40 gnd v cc i/o0 i/o62 i/o63 i 5 v cc i/o3 i/o4 i/o5 i/o6 i/o1 i/o2 i/o61 i/o57 i/o58 i/o59 i/o60 i/o56 i/o7 gnd gnd v cc i 2 i/o34 i/o33 i/o32 v cc i/o29 i/o28 i/o27 i/o26 i/o31 i/o30 i/o35 i/o39 i/o38 i/o37 i/o36 gnd i/o25 i/o24 note: pin-compatible with mach130, mach131, mach230, and mach231 pin designations clk/i = clock or input gnd = ground i = input i/o = input/output v cc = supply voltage
4 mach435-12/15/20, q-20/25 ordering information commercial products p r o g r a m m a b l e l o g i c p r o d u c t s f o r c o m m e r c i a l a p p l i c a t i o n s a r e a v a i l a b l e w i t h s e v e r a l o r d e r i n g o p t i o n s . t h e o r d e r n u m b e r (valid combination) is formed by a combination of: operating conditions c = commercial (0 c to +70 c) family type mach = macro array cmos high-speed speed -12 = 1 2 ns t pd -15 = 15 ns t pd -20 = 20 ns t pd -25 = 25 ns t pd mach435-12 mach435-15 mach435-20 mach435q-20 mach435q-25 mach -12 j c valid combinations the valid combinations table lists configurations planned to be supported in volume for this device. c o n s u l t your local sales office to confirm availabil- ity of specific valid combinations and to check on newly released combinations. valid combinations optional processing blank = standard processing 435 device number 435 = 2nd generation, 128 macrocells, 84 pins 435q = 2nd generation, 128 macrocells, 84 pins, quarter power package type j = 84-pin plastic leaded chip carrier (pl 084) jc
5 mach435-12/15/20, q-20/25 functional description the mach435 consists of eight pal blocks connected by a central switch matrix. there are 64 i/o pins and 6 dedicated input pins feeding the central switch matrix. these signals are distributed to the eight pal blocks for efficient design implementation. there are 4 global clock pins that can also be used as dedicated inputs. all inputs and i/o pins have built-in pull-up resistors. while it is always good design practice to tie unused pins high, the pull-up resistors provide design security and stability in the event that unused pins are left disconnected. the pal blocks each pal block in the mach435 (figure 1) contains a clock generator, a 90-product-term logic array, a logic allocator, 16 macrocells, an output switch matrix, 8 i/o cells, and an input switch matrix. the central switch matrix feeds each pal block with 33 inputs. this makes the pal block look effectively like an independent pal33v16 with 8 to 16 buried macrocells. in addition to the logic product terms, individual output enable product terms and two pal block initialization product term are provided. each i/o pin can be individually enabled. all flip-flops that are in the synchronous mode within a pal block are initialized together by either of the pal block initialization product terms. the central switch matrix and input switch matrix the mach435 central switch matrix is fed by the input switch matrices in each pal block. each pal block provides 16 internal feedback signals, 8 registered input signals, and 8 i/o pin signals to the input switch matrix. of these 32 signals, 24 decoded signals are provided to the central switch matrix by the input switch matrix. the central switch matrix distributes these signals back to the pal blocks in a very efficient manner that provides for high performance. the design software automati- cally configures the input and central switch matrices when fitting a design into the device. the clock generator each pal block has a clock generator that can generate four clock signals for use throughout the pal block. these four signals are available to all macrocells and i/o cells in the pal block, whether in synchronous or asynchronous mode. the clock generator chooses the four signals from the eight possible signals given by the true and complement versions of the four global clock pin signals. the product-term array the mach435 product-term array consists of 80 product terms for logic use, eight product terms for output enable use, and two product terms for global pal block initialization. each macrocell has a nominal allocation of 5 product terms for logic, although the logic allocator allows for logic redistribution. each i/o pin has its own individual output enable term. the initialization product terms provide asynchronous reset or preset to synchronous-mode macrocells in the pal block. the logic allocator the logic allocator in the mach435 takes the 80 logic product terms and allocates them to the 16 macrocells as needed. each macrocell can be driven by up to 20 product terms if in synchronous mode, or 18 product terms if in asynchronous mode. when product terms are routed away from a macrocell, it is possible to route all 5 product terms away, which precludes the use of the macrocell for logic generation; or it is possible to route only 4 product terms away, leaving one for simple function generation. the design software automatically configures the logic allocator when fitting the design into the device. the logic allocator also provides an exclusive-or gate. this gate allows generation of combinatorial exclusive- or logic, such as comparison or addition. it allows registered exclusive-or functions, such as crc gen- eration, to be implemented more efficiently. it also makes in possible to emulate all flip-flop types with a d-type flip-flop. register type emulation is automatically handled by the design software. table 1 illustrates which product term clusters are available to each macrocell within a pal block. refer to figure 1 for cluster and macrocell numbers.
6 mach435-12/15/20, q-20/25 table 1. logic allocation macrocell available clusters m0 c0, c1, c2 m1 c0, c1, c2, c3 m2 c1, c2, c3, c4 m3 c2, c3, c4, c5 m4 c3, c4, c5, c6 m5 c4, c5, c6, c7 m6 c5, c6, c7, c8 m7 c6, c7, c8, c9 m8 c7, c8, c9, c10 m9 c8, c9, c10, c11 m10 c9, c10, c11, c12 m11 c10, c11, c12, c13 m12 c11, c12, c13, c14 m13 c12, c13, c14, c15 m14 c13, c14, c15 m15 c14, c15 the macrocell and output switch matrix the mach435 has 16 macrocells, half of which can drive i/o pins; this selection is made by the output switch matrix. each macrocell can drive one of four i/o cells. the allowed combinations are shown in table 2. please refer to figure 1 for macrocell and i/o pin numbers. table 2. output switch matrix combinations macrocell routable to i/o pins m0, m1 i/o5, i/o6, i/o7, i/o0 m2, m3 i/o6, i/o7, i/o0, i/o1 m4, m5 i/o7, i/o0, i/o1, i/o2 m6, m7 i/o0, i/o1, i/o2, i/o3 m8, m9 i/o1, i/o2, i/o3, i/o4 m10, m11 i/o2, i/o3, i/o4, i/o5 m12, m13 i/o3, i/o4, i/o5, i/o6 m14, m15 i/o4, i/o5, i/o6, i/o7 i/o pin available macrocells i/o0 m0, m1, m2, m3, m4, m5, m6, m7 i/o1 m2, m3, m4, m5, m6, m7, m8, m9 i/o2 m4, m5, m6, m7, m8, m9, m10, m11 i/o3 m6, m7, m8, m9, m10, m11, m12, m13 i/o4 m8, m9, m10, m11, m12, m13, m14, m15 i/o5 m10, m11, m12, m13, m14, m15, m0, m1 i/o6 m12, m13, m14, m15, m0, m1, m2, m3 i/o7 m14, m15, m0, m1, m2, m3, m4, m5 the macrocells can be configured as registered, latched, or combinatorial. in combination with the logic allocator, the registered configuration can be any of the standard flip-flop types. the macrocell provides internal feedback whether configured with or without the flip- flop, and whether or not the macrocell drives an i/o cell. the flip-flop clock depends on the mode selected for the macrocell. in synchronous mode, any of the pal block clocks generated by the clock generator can be used. in asynchronous mode, the additional choice of either edge of an individual product-term clock is available. initialization can be handled as part of a bank of macrocells via the pal block initialization terms if in synchronous mode, or individually if in asynchronous mode. in synchronous mode, one of the pal block product terms is available each for preset and reset. the swap function determines which product term drives which function. this allows initialization polarity com- patibility with the mach 1 and 2 series. in asynchronous mode, one product term can be used either to drive reset or preset. the i/o cell the i/o cell in the mach435 consists of a three-state buffer and an input flip-flop. the i/o cell is driven by one of the macrocells, as selected by the output switch matrix. each i/o cell can take its input from one of eight macrocells. the three-state buffer is controlled by an individual product term. the input flip-flop can be configured as a register or latch. both the direct i/o signal and the registered/latched signal are available to the input switch matrix, and can be used simultaneously if desired.
7 mach435-12/15/20, q-20/25 17469e-3 clock generator macrocell macrocell i/o cell macrocell macrocell macrocell macrocell macrocell macrocell macrocell macrocell macrocell macrocell macrocell macrocell macrocell macrocell output switch matrix logic allocator central switch matrix input switch matrix 24 16 16 4 17 16 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15 m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15 o0 o1 o2 o3 o4 o5 o6 o7 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell clk0/i0 clk1/i1 clk2/i3 clk3/i4 figure 1. mach435 pal block
8 mach435-12 (com'l) absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . supply voltage with respect to ground C0.5 v to +7.0 v. . . . . . . . . . . . . dc input voltage C0.5 v to v cc +0.5 v . . . . . . . . . . . . dc output or i/o pin voltage C0.5 v to v cc +0.5 v . . . . . . . . . . . . . static discharge voltage 2001 v . . . . . . . . . . . . . . . . . latchup current (t a = 0 c to +70 c) 200 ma . . . . . . . . . . . . . . . . . . . . operating ranges commercial (c) devices temperature (t a ) operating in free air 0 c to +70 c . . . . . . . . . . . . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.75 v to +5.25 v . . . . . . . . . . . . operating ranges define those limits between which the functionality of the device is guaranteed. stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. programming conditions may differ. dc characteristics over commercial operating ranges unless otherwise specified parameter symbol parameter description test conditions min typ max unit v oh output high voltage i oh = C3.2 ma, v cc = min 2.4 v v in = v ih or v il v ol output low voltage i ol = 24 ma, v cc = min 0.5 v v in = v ih or v il (note 1) v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 2) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 2) i ih input high leakage current v in = 5.25 v, v cc = max (note 3) 10 m a i il input low leakage current v in = 0 v, v cc = max (note 3) C100 m a i ozh off-state output leakage v out = 5.25 v, v cc = max current high v in = v ih or v il (note 3) i ozl off-state output leakage v out = 0 v, v cc = max current low v in = v ih or v il (note 3) i sc output short-circuit current v out = 0.5 v, v cc = max (note 4) C30 C160 ma i cc supply current (typical) v in = 0 v, outputs open (i out = 0 ma) 255 ma v cc = 5.0 v, f =25 mhz, t a = 25 c (note 5) m a m a 10 C100 capacitance (note 6) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c, 6 p f c out output capacitance v out = 2.0 v f = 1 mhz 8 p f notes: 1. total i ol for one pal block should not exceed 128 ma. 2. these are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 3. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 4. not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 5. measured with a 16-bit up/down counter pattern. this pattern is programmed in each pal block and capable of being loaded, enabled, and reset. 6. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
9 mach435-12 (com'l) switching characteristics over commercial operating ranges (note 1) parameter symbol parameter description min max unit t pd input, i/o, or feedback to combinatorial output 3 1 2 n s setup time from input, i/o, or d-type 5 ns t-type 6 n s t ha register data hold time using product term clock 5 n s t coa product term clock to output 4 1 4 n s t wla low 8 n s t wha high 8 n s d-type 52.6 mhz t-type 50 mhz d-type 58.8 mhz t-type 55.6 mhz 62.5 mhz t ss d-type 7 n s t-type 8 n s t hs register data hold time using global clock 0 n s t cos global clock to output 2 8 ns t wls low 6 n s t whs high 6 n s d-type 66.7 mhz t-type 62.5 mhz f maxs d-type 83.3 mhz t-type 76.9 mhz 83.3 mhz t sla setup time from input, i/o, or feedback to 5 n s product term clock t hla latch data hold time using product term clock 5 n s t goa product term gate to output 16 ns t gwa product term gate width low (for low transparent) 6 n s or high (for high transparent) t sls setup time from input, i/o, or feedback to global gate 8 n s t hls latch data hold time using global gate 0 n s t gos gate to output 10 ns t gws global gate width low (for low transparent) 6 n s or high (for high transparent) t pdl input, i/o, or feedback to output through transparent input or output latch 14 ns t sir input register setup time 2 n s t hir input register hold time 3 n s t ico input register clock to combinatorial output 18 ns external feedback internal feedback (f cnta ) no feedback (note 3) global clock width feedback to product term clock -12 t sa f maxa product term, clock width maximum frequency using product term clock (note 2) external feedback setup time from input, i/o, or feedback to global clock internal feedback (f cnta ) no feedback (note 3) maximum frequency using global clock (note 2)
10 mach435-12 (com'l) switching characteristics over commercial operating ranges (note 1) (continued) parameter symbol parameter description min max unit t ics input register clock to output register setup d-type 9 n s t-type 10 ns t wicl low 6 n s t wich high 6 n s f maxir maximum input register frequency 83.3 mhz t sil input latch setup time 2 n s t hil input latch hold time 3 n s t igo input latch gate to combinatorial output 16 ns t igol input latch gate to output through transparent output latch 18 ns setup time from input, i/o, or feedback through t slla transparent input latch to product term output 4 n s latch gate t igsa input latch gate to output latch setup using 4 n s product term output latch gate t slls setup time from input, i/o, or feedback through transparent input latch to global output latch gate 9 n s t igss input latch gate to output latch setup using global 9 n s output latch gate t wigl input latch gate width low 6 n s t pdll input, i/o, or feedback to output through transparent input and output latches 16 ns t ar asynchronous reset to registered or latched output 16 ns t arw asynchronous reset width (note 1) 12 ns t arr asynchronous reset recovery time (note 1) 10 ns t ap asynchronous preset to registered or latched output 16 ns t apw asynchronous preset width (note 1) 12 ns t apr asynchronous preset recovery time (note 1) 8 n s t ea input, i/o, or feedback to output enable 2 1 2 n s t er input, i/o, or feedback to output disable 2 1 2 n s notes: 1. see switching test circuit at the end of this data book for test conditions. 2. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 3. this parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. input register clock width -12
11 mach435-15/20 (com'l) absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . supply voltage with respect to ground C0.5 v to +7.0 v . . . . . . . . . . . . . dc input voltage C0.5 v to v cc +0.5 v . . . . . . . . . . . . dc output or i/o pin voltage C0.5 v to v cc +0.5 v . . . . . . . . . . . . . static discharge voltage 2001 v . . . . . . . . . . . . . . . . . latchup current (t a = 0 c to +70 c) 200 ma . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. programming conditions may differ. operating ranges commercial (c) devices temperature (t a ) operating in free air 0 c to +70 c . . . . . . . . . . . . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.75 v to +5.25 v . . . . . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating ranges unless otherwise specified parameter symbol parameter description test conditions min typ max unit v oh output high voltage i oh = C3.2 ma, v cc = min 2.4 v v in = v ih or v il v ol output low voltage i ol = 24 ma, v cc = min 0.5 v v in = v ih or v il (note 1) v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 2) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 2) i ih input high leakage current v in = 5.25 v, v cc = max (note 3) 10 m a i il input low leakage current v in = 0 v, v cc = max (note 3) C100 m a i ozh off-state output leakage v out = 5.25 v, v cc = max 10 m a current high v in = v ih or v il (note 3) i ozl off-state output leakage v out = 0 v, v cc = max current low v in = v ih or v il (note 3) i sc output short-circuit current v out = 0.5 v, v cc = max (note 4) C30 C160 ma i cc supply current v in = 0 v, outputs open 255 ma (i out = 0 ma), v cc = 5.0 v, f =25 mhz, t a = 25 c (note 5) m a C100 capacitance (note 6) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c, 6 p f c out output capacitance v out = 2.0 v f = 1 mhz 8 p f notes: 1. total i ol for one pal block should not exceed 128 ma. 2. these are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 3. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 4. not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 5. measured with a 16-bit up/down counter pattern. this pattern is programmed in each pal block and capable of being loaded, enabled, and reset. an actual i cc value can be calculated by using the typical dynamic i cc characteristics chart towards the end of this data sheet. 6. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
12 mach435-15/20 (com'l) switching characteristics over commercial operating ranges (note 1) parameter symbol parameter description min max min max unit t pd input, i/o, or feedback to combinatorial output (note 2) 3 1 5 3 20 ns d-type 8 1 0 n s t-type 9 1 1 n s t ha register data hold time using product term clock 8 1 0 n s t coa product term clock to output (note 2) 4 1 8 4 22 ns t wla low 9 1 2 n s t wha high 9 1 2 n s d-type 38.5 31.2 mhz t-type 37 30.3 mhz d-type 47.6 37 mhz t-type 45.4 35.7 mhz 55.6 41.7 mhz t ss d-type 10 13 ns t-type 11 14 ns t hs register data hold time using global clock 0 0 ns t cos global clock to output (note 2) 2 1 0 2 12 ns t wls low 6 8 ns t whs high 6 8 ns d-type 50 40 mhz t-type 47.6 38.5 mhz f maxs d-type 66.6 50 mhz t-type 62.5 47.6 mhz 83.3 62.5 mhz t sla setup time from input, i/o, or feedback to 8 1 0 n s product term clock t hla latch data hold time using product term clock 8 1 0 n s t goa product term gate to output (note 2) 19 22 ns t gwa product term gate width low (for low transparent) 9 1 2 n s or high (for high transparent) t sls setup time from input, i/o, or feedback to global gate 10 13 ns t hls latch data hold time using global gate 0 0 ns t gos gate to output (note 2) 11 12 ns t gws global gate width low (for low transparent) 6 8 ns or high (for high transparent) t pdl input, i/o, or feedback to output through transparent input or output latch 17 22 ns t sir input register setup time 2 2 ns t hir input register hold time 4 5 ns t ico input register clock to combinatorial output 20 25 ns no feedback 1/(t wls + t whs ) (note 4) maximum frequency using global clock (note 3) external feedback 1/(t sa + t coa ) internal feedback (f cnta ) no feedback 1/(t wla + t wha ) (note 4) global clock width setup time from input, i/o, or feedback to product term clock -15 -20 t sa f maxa product term, clock width maximum frequency using product term clock (note 3) external feedback 1/(t ss + t cos ) internal feedback (f cnts ) setup time from input, i/o, or feedback to global clock
13 mach435-15/20 (com'l) switching characteristics over commercial operating ranges (note 1) (continued) parameter symbol parameter description min max min max unit t ics input register clock to output register setup d-type 15 20 ns t-type 16 21 ns t wicl low 6 8 ns t wich high 6 8 ns f maxir maximum input register frequency 1/(t wicl + t wich ) 83.3 62.5 mhz t sil input latch setup time 2 2 ns t hil input latch hold time 4 5 ns t igo input latch gate to combinatorial output 20 25 ns t igol input latch gate to output through transparent output latch 22 27 ns setup time from input, i/o, or feedback through t slla transparent input latch to product term output latch gate 10 12 ns t igsa input latch gate to output latch setup using product term output latch gate 14 19 ns t slls setup time from input, i/o, or feedback through transparent input latch to global output latch gate 12 16 ns t igss input latch gate to output latch setup using global output latch gate 16 21 ns t wigl input latch gate width low 6 8 ns t pdll input, i/o, or feedback to output through transparent input and output latches 19 24 ns t ar asynchronous reset to registered or latched output 20 25 ns t arw asynchronous reset width (note 3) 15 20 ns t arr asynchronous reset recovery time (note 3) 15 20 ns t ap asynchronous preset to registered or latched output 20 25 ns t apw asynchronous preset width (note 3) 15 20 ns t apr asynchronous preset recovery time (note 3) 15 20 ns t ea input, i/o, or feedback to output enable (note 2) 2 1 5 2 20 ns t er input, i/o, or feedback to output disable (note 2) 2 1 5 2 20 ns -15 -20 input register clock width notes: 1. see switching test circuit at the end of this data book for test conditions. 2. parameters measured with 32 outputs switching. 3. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 4. this parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.
14 mach435q-20 (com'l) absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . supply voltage with respect to ground C0.5 v to +7.0 v. . . . . . . . . . . . . dc input voltage C0.5 v to v cc +0.5 v . . . . . . . . . . . . dc output or i/o pin voltage C0.5 v to v cc +0.5 v . . . . . . . . . . . . . static discharge voltage 2001 v . . . . . . . . . . . . . . . . . latchup current (t a = 0 c to +70 c) 200 ma . . . . . . . . . . . . . . . . . . . . operating ranges commercial (c) devices temperature (t a ) operating in free air 0 c to +70 c . . . . . . . . . . . . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.75 v to +5.25 v . . . . . . . . . . . . operating ranges define those limits between which the functionality of the device is guaranteed. stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. programming conditions may differ. dc characteristics over commercial operating ranges unless otherwise specified parameter symbol parameter description test conditions min typ max unit v oh output high voltage i oh = C3.2 ma, v cc = min 2.4 v v in = v ih or v il v ol output low voltage i ol = 24 ma, v cc = min 0.5 v v in = v ih or v il (note 1) v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 2) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 2) i ih input high leakage current v in = 5.25 v, v cc = max (note 3) 10 m a i il input low leakage current v in = 0 v, v cc = max (note 3) C100 m a i ozh off-state output leakage v out = 5.25 v, v cc = max current high v in = v ih or v il (note 3) i ozl off-state output leakage v out = 0 v, v cc = max current low v in = v ih or v il (note 3) i sc output short-circuit current v out = 0.5 v, v cc = max (note 4) C30 C160 ma i cc supply current (typical) v in = 0 v, outputs open (i out = 0 ma) 115 ma v cc = 5.0 v, f =25 mhz, t a = 25 c (note 5) m a m a 10 C100 capacitance (note 6) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c, 6 p f c out output capacitance v out = 2.0 v f = 1 mhz 8 p f notes: 1. total i ol for one pal block should not exceed 128 ma. 2. these are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 3. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 4. not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 5. measured with a 16-bit up/down counter pattern. this pattern is programmed in each pal block and capable of being loaded, enabled, and reset. 6. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
15 mach435q-20 (com'l) switching characteristics over commercial operating ranges (note 1) parameter symbol parameter description min max unit t pd input, i/o, or feedback to combinatorial output 3 2 0 n s setup time from input, i/o, or d-type 10 ns t-type 11 ns t ha register data hold time using product term clock 16 ns t coa product term clock to output 5 2 2 n s t wla low 12 ns t wha high 12 ns d-type 33.3 mhz t-type 37.2 mhz d-type 35.7 mhz t-type 34.5 mhz 41.7 mhz t ss d-type 13 ns t-type 14 ns t hs register data hold time using global clock 0 n s t cos global clock to output 2 1 2 n s t wls low 8 n s t whs high 8 n s d-type 40.0 mhz t-type 38.5 mhz f maxs d-type 47.6 mhz t-type 43.5 mhz 62.5 mhz t sla setup time from input, i/o, or feedback to 8 n s product term clock t hla latch data hold time using product term clock 8 n s t goa product term gate to output 22 ns t gwa product term gate width low (for low transparent) 12 ns or high (for high transparent) t sls setup time from input, i/o, or feedback to global gate 13 ns t hls latch data hold time using global gate 0 n s t gos gate to output 12 ns t gws global gate width low (for low transparent) 8 n s or high (for high transparent) t pdl input, i/o, or feedback to output through transparent input or output latch 22 ns t sir input register setup time 2 n s t hir input register hold time 4 n s t ico input register clock to combinatorial output 22 ns external feedback internal feedback (f cnta ) no feedback (note 3) global clock width feedback to product term clock -20 t sa f maxa product term, clock width maximum frequency using product term clock (note 2) external feedback setup time from input, i/o, or feedback to global clock internal feedback (f cnta ) no feedback (note 3) maximum frequency using global clock (note 2)
16 mach435q-20 (com'l) switching characteristics over commercial operating ranges (note 1) (continued) parameter symbol parameter description min max unit t ics input register clock to output register setup d-type 15 ns t-type 17 ns t wicl low 8 n s t wich high 8 n s f maxir maximum input register frequency 62.5 mhz t sil input latch setup time 2 n s t hil input latch hold time 2.5 ns t igo input latch gate to combinatorial output 22 ns t igol input latch gate to output through transparent output latch 24 ns setup time from input, i/o, or feedback through t slla transparent input latch to product term output 12 ns latch gate t igsa input latch gate to output latch setup using 10 ns product term output latch gate t slls setup time from input, i/o, or feedback through transparent input latch to global output latch gate 15 ns t igss input latch gate to output latch setup using global 15 ns output latch gate t wigl input latch gate width low or high 8 n s t pdll input, i/o, or feedback to output through transparent input and output latches 24 ns t ar asynchronous reset to registered or latched output 25 ns t arw asynchronous reset width (note 1) 20 ns t arr asynchronous reset recovery time (note 1) 15 ns t ap asynchronous preset to registered or latched output 25 ns t apw asynchronous preset width (note 1) 20 ns t apr asynchronous preset recovery time (note 1) 15 ns t ea input, i/o, or feedback to output enable 2 2 0 n s t er input, i/o, or feedback to output disable 2 2 0 n s notes: 1. see switching test circuit at the end of this data book for test conditions. 2. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 3. this parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. input register clock width -20
mach435q-25 (com'l) 17 absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . supply voltage with respect to ground C0.5 v to +7.0 v. . . . . . . . . . . . . dc input voltage C0.5 v to v cc +0.5 v. . . . . . . . . . . dc output or i/o pin voltage C0.5 v to v cc +0.5 v. . . . . . . . . . . . static discharge voltage 2001 v . . . . . . . . . . . . . . . . . latchup current (t a = 0 c to +70 c) 200 ma . . . . . . . . . . . . . . . . . . . . operating ranges commercial (c) devices temperature (t a ) operating in free air 0 c to +70 c . . . . . . . . . . . . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.75 v to +5.25 v . . . . . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. programming conditions may differ. dc characteristics over commercial operating ranges unless otherwise specified parameter symbol parameter description test conditions min typ max unit v oh output high voltage i oh = C3.2 ma, v cc = min 2.4 v v in = v ih or v il v ol output low voltage i ol = 24 ma, v cc = min 0.5 v v in = v ih or v il (note 1) v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 2) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 2) i ih input high leakage current v in = 5.25 v, v cc = max (note 3) 10 m a i il input low leakage current v in = 0 v, v cc = max (note 3) C100 m a i ozh off-state output leakage v out = 5.25 v, v cc = max current high v in = v ih or v il (note 3) i ozl off-state output leakage v out = 0 v, v cc = max current low v in = v ih or v il (note 3) i sc output short-circuit current v out = 0.5 v, v cc = max (note 4) C30 C160 ma i cc supply current v in = 0 v, outputs open 115 ma (i out = 0 ma), v cc = 5.0 v, f=25 mhz, t a = 25 c, (note 5) m a m a 10 C100 capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c, 6 p f c out output capacitance v out = 2.0 v f = 1 mhz 8 p f notes: 1. total i ol for one pal block should not exceed 128 ma. 2. these are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 3. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 4. not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 5. measured with a 16-bit up/down counter pattern. this pattern is programmed in each pal block and capable of being loaded, erased, and reset. an actual i cc value can be calculated by using the typical dynamic i cc characteristics chart towards the end of the this data sheet. 6. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
mach435q-25 (com'l) 18 switching characteristics over commercial operating ranges (note 1) parameter symbol parameter description min max unit t pd input, i/o, or feedback to combinatorial output (note 2) 325ns d-type 18 ns t-type 19 ns t ha register data hold time using product term clock 18 ns t coa product term clock to output (note 2) 4 2 8 n s t wla low 19 ns t wha high 19 ns d-type 21.7 mhz t-type 21.3 mhz d-type 24.4 mhz t-type 23.8 mhz 26.3 mhz t ss d-type 20 ns t-type 21 ns t hs register data hold time using global clock 0 n s t cos global clock to output (note 2) 2 1 2 n s t wls low 8 n s t whs high 8 n s d-type 31.3 mhz t-type 30.3 mhz f maxs d-type 37 mhz t-type 35.7 mhz 50 mhz t sla setup time from input, i/o, or feedback to 18 ns product term clock t hla latch data hold time using product term clock 18 ns t goa product term gate to output (note 2) 29 ns t gwa product term gate width low (for low transparent) 19 ns or high (for high transparent) t sls setup time from input, i/o, or feedback to global gate 20 ns t hls latch data hold time using global gate 0 n s t gos gate to output (note 2) 21 ns t gws global gate width low (for low transparent) 8 n s or high (for high transparent) t pdl input, i/o, or feedback to output through transparent input or output latch 27 ns t sir input register setup time 5 n s t hir input register hold time 5 n s t ico input register clock to combinatorial output 30 ns -25 maximum frequency using global clock (note 3) external feedback 1/(t sa + t coa ) internal feedback (f cnta ) no feedback 1/(t wla + t wha ) (note 4) global clock width setup time from input, i/o, or feedback to product term clock t sa f maxa product term, clock width maximum frequency using product term clock (note 3) external feedback 1/(t ss + t cos ) internal feedback (f cnts ) no feedback 1/(t ss + t hs ) (note 4) setup time from input, i/o, or feedback to global clock
mach435q-25 (com'l) 19 switching characteristics over commercial operating ranges (note 1) (continued) parameter symbol parameter description min max unit t ics input register clock to output register setup d-type 25 ns t-type 26 ns t wicl low 8 n s t wich high 8 n s f maxir maximum input register frequency 1/(t wicl + t wich ) 62.5 mhz t sil input latch setup time 5 n s t hil input latch hold time 5 n s t igo input latch gate to combinatorial output 30 ns t igol input latch gate to output through transparent output latch 32 ns setup time from input, i/o, or feedback through t slla transparent input latch to product term output latch gate 20 ns t igsa input latch gate to output latch setup using product term output latch gate 24 ns t slls setup time from input, i/o, or feedback through transparent input latch to global output latch gate 22 ns t igss input latch gate to output latch setup using global output latch gate 26 ns t wigl input latch gate width low or high 8 n s t pdll input, i/o, or feedback to output through transparent input and output latches 29 ns t ar asynchronous reset to registered or latched output 30 ns t arw asynchronous reset width (note 3) 25 ns t arr asynchronous reset recovery time (note 3) 25 ns t ap asynchronous preset to registered or latched output 30 ns t apw asynchronous preset width (note 3) 25 ns t apr asynchronous preset recovery time (note 3) 25 ns t ea input, i/o, or feedback to output enable (note 2) 2 2 5 n s t er input, i/o, or feedback to output disable (note 2) 2 2 5 n s -25 input register clock width notes: 1. see switching test circuit at the end of this data book for test conditions. 2. parameters measured with 32 outputs switching. 3. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 4. this parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.
20 mach435-12/15/20, q-20/25 typical current vs. voltage (i-v) characteristics v cc = 5.0 v, t a = 25 c input 20 C40 C60 C80 C2 C1 123 output, high i i (ma) v i (v) C20 i oh (ma) v oh (v) 25 C50 C75 C100 C3 C2 C1 123 C25 C125 C150 45 45 C100 C0.8 C0.6 C0.4 .2 C0.2C1.0 output, low .4 .6 1.0 .8 60 40 20 C20 C40 80 C60 C80 i ol (ma) v ol (v) 17469e-4 17469e-5 17469e-6
21 mach435-12/15/20, q-20/25 typical i cc characteristics v cc = 5 v, t a = 25 c i cc (ma) 0 10 203040 506070 frequency (mhz) 325 300 275 250 225 200 175 150 125 100 75 50 25 0 mach435q mach435 the selected typical pattern is a 16-bit up/down counter. this pattern is programmed in each pal block and is capable of being loaded, enabled, and reset. maximum frequency shown uses internal feedback and a d-type register. 17469e-7
22 mach435-12/15/20, q-20/25 typical thermal characteristics measured at 25 c ambient. these parameters are not tested. parameter symbol parameter description plcc unit q jc thermal impedance, junction to case 5 c/w q ja thermal impedance, junction to ambient 20 c/w q jma thermal impedance, junction to ambient with air flow 200 lfpm air 17 c/w 400 lfpm air 14 c/w 600 lfpm air 12 c/w 800 lfpm air 10 c/w plastic q jc considerations the data listed for plastic q jc are for reference only and are not recommended for use in calculating junction temperatures. the heat-flow paths in plastic-encapsulated devices are complex, making the q jc measurement relative to a specific location on the package surface. tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. furthermore, q jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. therefore, the measurements can only be used in a similar environment. typ
23 mach435-12/15/20, q-20/25 switching waveforms notes: 1. v t = 1.5 v. 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 nsC4 ns typical. t pd input, i/o, or feedback combinatorial output v t v t combinatorial output v t input, i/o, or feed- back registered output registered output t s t co v t t h v t clock t wh clock clock width t wl v t combinatorial output registered input (mach 2 and 4) t sir t ico v t t hir v t input register clock registered input latched output (mach 2, 3, and 4) gate gate width (mach 2, 3, and 4) t gws v t v t v t v t t ics input register to output register setup (mach 2 and 4) output register clock input register clock registered input t pdl input, i/o, or feedback latched out gate v t t hl t sl t go v t v t 17469e-8 17469e-9 17469e-10 17469e-11 17469e-12 17469e-13 17469e-14
24 mach435-12/15/20, q-20/25 switching waveforms notes: 1. v t = 1.5 v. 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 nsC4 ns typical. latched input (mach 2 and 4) latched input and output (mach 2, 3, and 4) latched in output latch gate latched out t sll combinatorial output gate t hil t sil t igo latched in t pdll t igol t igs input latch gate v t v t v t v t v t v t 17469e-15 17469e-16
25 mach435-12/15/20, q-20/25 switching waveforms t wich clock input register clock width (mach 2 and 4) v t t wicl v t v t t arw v t t ar asynchronous reset input, i/o, or feedback registered output clock t arr asynchronous preset registered output clock v t v t outputs output disable/enable t er t ea v oh - 0.5v v ol + 0.5v notes: 1. v t = 1.5 v. 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 nsC4 ns typical. input, i/o, or feedback v t v t input, i/o, or feedback t apw v t t ap t apr input latch gate input latch gate width (mach 2 and 4) t wigl v t 17469e-17 17469e-18 17469e-19 17469e-20 17469e-21
26 mach435-12/15/20, q-20/25 key to switching waveforms ks000010-pal must be steady may change from h to l may change from l to h does not apply don't care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs switching test circuit measured specification s 1 c l r 1 r 2 output value t pd , t co closed 1.5 v t ea z ? h: open 35 pf 1.5 v z ? l: closed 300 w 390 w t er h ? z: open 5 pf h ? z: v oh C 0.5 v l ? z: closed l ? z: v ol + 0.5 v commercial 17469e-22 c l output r 1 r 2 s 1 test point 5 v *switching several outputs simultaneously should be avoided for accurate measurement.
28 mach435-12/15/20, q-20/25 endurance characteristics the mach families are manufactured using ou r advanced electrically erasable process. this technol- ogy uses an ee cell to replace the fuse link used in bipolar parts. as a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. endurance characteristics parameter symbol parameter description min units test conditions 10 years max storage temperature 20 years max operating temperature n max reprogramming cycles 100 cycles normal programming conditions t dr min pattern data retention time
29 mach435-12/15/20, q-20/25 input/output equivalent schematics input i/o preload circuitry esd protection feedback input v cc v cc 1 k w 100 k w v cc v cc 100 k w 1 k w 17469e-24
30 mach435-12/15/20, q-20/25 power-up reset the mach devices have been designed with the capa- bility to reset during system power-up. following power- up, all flip-flops will be reset to low. the output state will depend on the logic polarity. this feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. a timing dia- gram and parameter table are shown below. due to the synchronous operation of the power-up reset and the wide range of ways v cc can rise to its steady state, two conditions are required to insure a valid power-up reset. these conditions are: 1. the v cc rise must be monotonic. 2. following reset, the clock input must not be driven from low to high until all applicable input and feedback setup times are met. parameter symbol parameter descriptions max unit t pr power-up reset time 10 m s t s input or feedback setup time t wl clock width low see switching characteristics t pr t wl t s 4 v v cc power registered output clock 17469e-25 power-up reset waveform
31 mach435-12/15/20, q-20/25 using preload and observability in order to be testable, a circuit must be both controllable and observable. to achieve this, the mach devices incorporate register preload and observability. in preload mode, each flip-flop in the mach device can be loaded from the i/o pins, in order to perform functional testing of complex state machines. register preload makes it possible to run a series of tests from a known starting state, or to load illegal states and test for proper recovery. this ability to control the mach device's internal state can shorten test sequences, since it is easier to reach the state of interest. the observability function makes it possible to see the internal state of the buried registers during test by overriding each register's output enable and activating the output buffer. the values stored in output and buried registers can then be observed on the i/o pins. without this feature, a thorough functional test would be impossible for any designs with buried registers. while the implementation of the testability features is fairly straightforward, care must be taken in certain instances to insure valid testing. one case involves asynchronous reset and preset. if the mach registers drive asynchronous reset or preset lines and are preloaded in such a way that reset or preset are asserted, the reset or preset may remove the preloaded data. this is illustrated in figure 2. care should be taken when planning functional tests, so that states that will cause unexpected resets and presets are not preloaded. another case to be aware of arises in testing combinato- rial logic. when an output is configured as combinato- rial, the observability feature forces the output into registered mode. when this happens, all product terms are forced to zero, which eliminates all combinatorial data. for a straight combinatorial output, the correct value will be restored after the preload or observe function, and there will be no problem. if the function implements a combinatorial latch, however, it relies on feedback to hold the correct value, as shown in figure 3. as this value may change during the preload or observe operation, you cannot count on the data being correct after the operation. to insure valid testing in these cases, outputs that are combinatorial latches should not be tested immediately following a preload or observe sequence, but should first be restored to a known state. all mach 2 devices support both preload and observability. contact individual programming vendors in order to verify programmer support. ar figure 2. preload/reset conflict q 1 on off preload mode q 2 ar preloaded high d q q 1 d q ar preloaded high q 2 17469e-26 figure 3. combinatorial latch set reset 17469e-27

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